On 15.04.19 15:44, John David Anglin wrote: > On 2019-04-15 8:43 a.m., Helge Deller wrote: >> On 15.04.19 01:20, John David Anglin wrote: >>> There are only a couple of instructions that can function as a memory barrier on >>> parisc. Currently, we use the sync instruction as a memory barrier when releasing >>> a spinlock. However, the ldcw instruction is a better barrier when we have a >>> handy memory location since it operates in the cache on coherent machines. >>> >>> This patch updates the spinlock release code to use ldcw. >> Just out of curiosity: Did you maye do any timing with that patch? > No, but I think it made 800 MHz rp3440 nearly as fast as 1 GHz c8000 based on buildd times. >> >> Secondly: >> >>> /* Release pa_tlb_lock lock without reloading lock address. */ >>> - .macro tlb_unlock0 spc,tmp >>> + .macro tlb_unlock0 spc,tmp,tmp1 >> Above you add the tmp1 variable... >> >>> #ifdef CONFIG_SMP >>> 98: or,COND(=) %r0,\spc,%r0 >>> - stw,ma \spc,0(\tmp) >>> + LDCW 0(\tmp),\tmp1 >> couldn't instead %r0 be used as register target in all ldcw() >> accesses you added as barriers? >> Or would the processor "optimize" the access away (which I doubt)? > No. See page 6-12 in PA 2.0 architecture manual. I had wondered > about it when I wrote the code. Ah, Ok! I've applied it to the for-next tree. Thanks! Helge
