On 11.11.2018 16:42, John David Anglin wrote:
> On 2018-11-09 4:04 p.m., Helge Deller wrote:
>> Signed-off-by: Helge Deller <deller@xxxxxx>
>>
>> diff --git a/arch/parisc/include/asm/barrier.h b/arch/parisc/include/asm/barrier.h
>> index dbaaca84f27f..43bcdccc56b8 100644
>> --- a/arch/parisc/include/asm/barrier.h
>> +++ b/arch/parisc/include/asm/barrier.h
>> @@ -6,7 +6,8 @@
>> /* The synchronize caches instruction executes as a nop on systems in
>> which all memory references are performed in order. */
>> -#define synchronize_caches() __asm__ __volatile__ ("sync" : : : "memory")
>> +#define synchronize_caches() asm volatile \
>> + ("sync" ALTERNATIVE(ALT_COND_NO_SMP, INSN_NOP) : : : "memory")
>> #if defined(CONFIG_SMP)
>> #define mb() do { synchronize_caches(); } while (0)
> Although this change is consistent with mb() on UP kernels, I'm thinking that it is wrong. That is
> the PA 2.0 out-of-order execution of memory accesses is likely visible on a UP machine when an
> interruption occurs. I think the UP and SMP defines for mb() need to be the same.
I think you are right with the fact that the sync-removals in this patch and the other one was wrong.
I'll resend the patch without touching sync in a few moments.
I'll keep the remaining patches in my for-next-next git branch.
Helge
