On 2018-10-17 10:52 AM, Helge Deller wrote:
4.19.0-rc7-64bit+ (all for-next patches incl. Dave's, but without alternative patching): (vmlinuz-4.19-rc7-noalternative)
[ 1.233597] CPU(s): 1 out of 1 PA8900 (Shortfin) at 800.002200 MHz online
[ 1.243121] Whole cache flush 4268326 cycles, flushing 19173376 bytes 2041619 cycles
[ 1.243137] Cache flush threshold set to 39145 KiB
[ 1.262504] Whole TLB flush 5430 cycles, Range flush 19173376 bytes 15324980 cycles
[ 1.262758] Calculated TLB flush threshold 8 KiB
[ 1.263126] TLB flush threshold set to 16 KiB
4.19.0-rc7-64bit+ (all for-next patches incl. Dave's and WITH alternative patching): (vmlinuz-4.19-rc7-for-next)
[ 1.181601] CPU(s): 1 out of 1 PA8900 (Shortfin) at 800.002200 MHz online
[ 2.662065] Whole cache flush 4287666 cycles, flushing 19169280 bytes 2040021 cycles
[ 2.662087] Cache flush threshold set to 39345 KiB
[ 2.663462] Whole TLB flush 7563 cycles, Range flush 19169280 bytes 940355 cycles
[ 2.663718] Calculated TLB flush threshold 152 KiB
[ 2.665174] TLB flush threshold set to 152 KiB
It is clear the pdtlb,l patching makes a huge difference in the range
flushing on rp3410. The number of
cycles goes from 15324980 to 940355. On c3750, the difference is about
100 cycles per page. We lack
numbers on rp5470.
So, we want pdtlb,l patching.
Dave
--
John David Anglin dave.anglin@xxxxxxxx
