Re: [PATCH] parisc: Reorder TLB flush timing calculation

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On 2018-09-23 11:20 AM, John David Anglin wrote:
I added a couple of information messages which I have left to help with
diagnosis if the problem should appear on another machine.
Looking at the calculated TLB flush thresholds, I see there is a large range of numbers.  The
most surprising numbers are for panama:

[    1.246425] Whole TLB flush 5982 cycles, Range flush 18874368 bytes 16515332 cycles
[    1.246680] Calculated TLB flush threshold 8 KiB
[    1.247120] TLB flush threshold set to 512 KiB

I don't know whether to believe the numbers or not.  But the whole cache flush seems to be amazingly fast compared to 4-way machines.  On the other hand, the range flush takes
4.25 times more cycles per byte than phantom.

Here are the numbers for phantom:

[    6.512604] Whole TLB flush 61861 cycles, Range flush 18874368 bytes 3876885 cycles
[    6.616030] Calculated TLB flush threshold 1180 KiB
[    6.680018] TLB flush threshold set to 1180 KiB

Both machines are PA8900 (Shortfin).  Panama is 800 MHz and phantom 1000 MHz.

Both have:
[    0.000000] Kernel default page size is 4 KB. Huge pages enabled with 1 MB physical and 2 MB virtual size.

It would appear the minimum TLB flush threshold needs to be reduced for machines like panama.

Dave

--
John David Anglin  dave.anglin@xxxxxxxx




[Index of Archives]     [Linux SoC]     [Linux USB Devel]     [Video for Linux]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]

  Powered by Linux