On Nov 3, 2015, at 3:03 PM, Helge Deller <deller@xxxxxx> wrote: > Sadly it's nowhere clearly documented how big the L1 cacheline of parisc really is. To which particular PA-RISC processor are you referring? It might not be the same on all processors. If openpa.net is to be believed, then: The 7100LC has 32 byte cache lines on the off-chip cache: http://www.openpa.net/pa-risc_processor_pa-7100lc.html and the 8500 has "32 or 64 Byte cache line size", which may be referring to the on-chip caches: http://www.openpa.net/pa-risc_processor_pa-8500.html-- To unsubscribe from this list: send the line "unsubscribe linux-parisc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
