On 2015-09-25 8:20 AM, John David Anglin wrote:
Our atomic_t types are guarded by ldcw locks. So, they are not really subject to contention.
You could be correct that L1_CACHE_BYTES could be reduced to 16 (i.e., maximum alignment
needed for any type on parisc) provided it isn't used somewhere where we need the actual L1
cache line size as returned by the PDC.
Digging through various documentation, I now believe that L1_CACHE_BYTES
is 16 bytes on ALL PA-RISC
processors. We are getting confused by the L2 length reported by the
PDC. The PA-8800 is essentially
two PA-8700s integrated on the same die.
See page 10 in this document:
https://parisc.wiki.kernel.org/images-parisc/e/e9/PA-8700wp.pdf
It shows the PA-8700 L1 design.
Dave
--
John David Anglin dave.anglin@xxxxxxxx
--
To unsubscribe from this list: send the line "unsubscribe linux-parisc" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
