04.09.2013, 23:54, "John David Anglin" <dave.anglin@xxxxxxxx>:
> Alex,
>
> That was the general idea although I was looking at the code in
> radeon_cp.c. I now think my suggestion
> was incorrect as the CP data is loaded via registers.
>
> After a bit of searching, I found a document which describes reading and
> writing to MicroEngine RAM.
> See page 22. I think we need to confirm after writing that we can read
> back the control program
> successfully.
>
> Dave
I disregarded this too, though WREG32 macro name evidently says that
it does writing to registers.
I'm touching the r100.c, as they've opted out a radeon_cp.c one.
Good find! I though that it would be worth to check the load somehow,
as well. I've added the following piece after the load:
WREG32(RADEON_CP_ME_RAM_RADDR, 0);
for (i = 0; i < size; i += 2)
if (RREG32(RADEON_CP_ME_RAM_DATAH)
!= be32_to_cpup(&fw_data[i]) ||
RREG32(RADEON_CP_ME_RAM_DATAL)
!= be32_to_cpup(&fw_data[i+1])) {
printk(KERN_WARNING "RADEON_CP_ME_RAM_DATAH "
"MISMATCH!\n");
break;
}
I've recompiled with this and booted to the new kernel, but seeing no warning,
so it looks like it passes.
What's strange though is why they write zero instead of concrete memory address
to the CP_ME_RAM_ADDR register...
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