On 26-Nov-11, at 7:35 PM, John David Anglin wrote:
On 25-Nov-11, at 10:18 PM, James Bottomley wrote:
I'm still a bit Jetlagged from a customer trip to Germany, but this
looks entirely possible: Appendix F says that a later TLB insertion
purges an earlier one, so I'd say in a combined I/D TLB inserting
consecutive I and D entries purges the I.
It looks like a fix might be to insert TLB entries supporting both
data
and instruction access in the combined TLB case.
In looking at the code, I couldn't see why the I and D entries would
differ.
Except for the dtlb_check_alias_20w check, the I and D handlers appear
identical. Maybe the hardware can't handle this case.
Don't understand this comment:
/*
* I miss is a little different, since we allow users to fault
* on the gateway page which is in the kernel address space.
*/
There is also a typo in this comment:
* Then incredible subtlety: The access rights are
* _PAGE_GATEWAY _PAGE_EXEC _PAGE_READ
I believe the last bit should be _PAGE_WRITE.
I just realized there is a difference. In the I case, va and spc are
loaded
from %pcoq and %pcsq, respectively. In the D case, they are loaded from
%ior and %isr. I haven't wrapped my head around this but space_adjust
may not be handling the b field correctly (D case)
Dave
--
John David Anglin dave.anglin@xxxxxxxx
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