On 24-Nov-11, at 8:16 AM, John David Anglin wrote:
So, my theory is there is a bug in the TLB miss handling. Somehow a
data miss ejects the instruction entry,
and we get into a loop inserting I and D TLB entries. Sometimes the
machine gets out of the loop but it takes
hours.
The TLB conf is:
D-TLB conf: sh 3 page 1 cst 1 aid 0 pad1 0
I-TLB conf: sh 3 page 1 cst 1 aid 3 pad1 0
I believe the sh value indicates either pitlb or pdtld may be used
(i.e., there is just one shared tlb) on rp3440.
Thus, the above scenario seems possible.
Dave
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John David Anglin dave.anglin@xxxxxxxx
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