On Thu, Dec 17, 2009 at 09:42:15AM -0800, Linus Torvalds wrote: > You both flush the virtual caches before > the IO and invalidate after - when the real pattern should be that you > flush it before a write, and invalidate it after a read. That's not entirely true. If you have write back caches which are not DMA coherent, you need to as a minimum: - on write, clean the cache to ensure that the page is up to date with data held in cache. - on read, you must ensure that there are no potential write-backs before the read commenses and invalidate at some point. The point at which you invalidate depends on whether the CPU speculatively prefetches: - If it doesn't, you can invalidate the cache before the read, thereby destroying any potential writebacks, and the cache will remain unallocated for that address range until explicitly accessed. - If you do have a CPU which does prefetch speculatively, then you do need to clean the cache before DMA starts, and then you must invalidate after the DMA completes. Invalidating after DMA completes for the non-speculative prefetch just wastes performance, especially if you have to do so line by line over a region. With ARM architecture version 7, we now have ARM CPUs which fall into both categories. -- Russell King Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/ maintainer of: -- To unsubscribe from this list: send the line "unsubscribe linux-parisc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
