On Tue, Nov 17, 2009 at 11:03:47AM -0600, James Bottomley wrote: > On Virtually Indexed architectures (which don't do automatic alias > resolution in their caches), we have to flush via the correct > virtual address to prepare pages for DMA. On some architectures > (like arm) we cannot prevent the CPU from doing data movein along > the alias (and thus giving stale read data), so we not only have to > introduce a flush API to push dirty cache lines out, but also an invalidate > API to kill inconsistent cache lines that may have moved in before > DMA changed the data The API looks right for MIPS and trivial to implement based on existing code, so feel free to throw in my Ack on the generic parts. The new APIs deserve documentation in Documentation/cachetlb.txt. Ralf -- To unsubscribe from this list: send the line "unsubscribe linux-parisc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
