Hi guys,
I am new to PARISC and to this forum. I have a small question. There is
an instruction in entry.S that I do not understand. It is in the the
macro make_insert_tlb
Kernel 2.6.26.2:
537 /* Enforce uncacheable pages.
538 * This should ONLY be use for MMIO on PA 2.0 machines.
539 * Memory/DMA is cache coherent on all PA2.0 machines we
support
540 * (that means T-class is NOT supported) and the memory
controllers
541 * on most of those machines only handles cache transactions.
542 */
543 extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
544 depi 1,12,1,\prot
The DEPI instruction on a 64-bit machine sets bit 44=32+12,
whereas we use the value as the argument to IDTLBT, which expects bit 12
to be used instead. Does it mean that the U-bit is never set and the
authorization id gets corrupted???
Is it a bug or my misunderstanding of the code???
Best regards,
Artem
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