> In this situation, the alignment of pdir's depends on how they
> were originally declared. If declared as long long, GCC will give
> them 8 byte alignment, so the two words should always be in the
> same cache line. On the otherhand, if the pdir is declared as
> a pair of 32-bit words, the pdir might span two cache lines.
It looks to me like pdirs should be 8 byte aligned and thus always
should lie in a cache line.
The following insn appears to put hints in the wrong place on
a 64-bit kernel since `pa' is then a 64-bit type:
asm volatile("depw %1,31,12,%0" : "+r" (pa) : "r" (hints));
The depw will operate on the left word. Looks like it should be
asm volatile("depw %1,31,12,%R0" : "+r" (pa) : "r" (hints));
when __LP64__ is defined. Think the same is true for the following
depw as well.
Dave
--
J. David Anglin dave.anglin@xxxxxxxxxxxxxx
National Research Council of Canada (613) 990-0752 (FAX: 952-6602)
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