From: Balaji T K <balajitk@xxxxxx>
Add support for sata controller.
[Roger Q] Clean up.
CC: Benoit Cousson <bcousson@xxxxxxxxxxxx>
Signed-off-by: Balaji T K <balajitk@xxxxxx>
Signed-off-by: Roger Quadros <rogerq@xxxxxx>
---
arch/arm/boot/dts/dra7.dtsi | 49 +++++++++++++++++++++++++++++++++++++++++++
1 files changed, 49 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index ce9a0f0..545545d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -426,6 +426,55 @@
dma-names = "tx", "rx";
};
+ omap_control_sata: control-phy@4a002374 {
+ compatible = "ti,control-phy-pipe3";
+ reg = <0x4a002374 0x4>;
+ reg-names = "power";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ };
+
+ ocp2scp3: ocp2scp3@4a090000 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "ocp2scp3";
+ reg = <0x4a090000 0x1f>; /* ocp2scp3 */
+ reg-names = "ocp2scp3";
+ sata_phy: sataphy@4A096000 {
+ compatible = "ti,phy-pipe3-sata";
+ reg = <0x4A096000 0x80>, /* phy_rx */
+ <0x4A096400 0x64>, /* phy_tx */
+ <0x4A096800 0x40>; /* pll_ctrl */
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ ctrl-module = <&omap_control_sata>;
+ clocks = <&sata_ref_clk>,
+ <&sys_clkin1>;
+ clock-names = "optclk", "sysclk";
+ #phy-cells = <0>;
+ };
+ };
+
+ sata: sata@4a141100 {
+ compatible = "ti,sata";
+ ti,hwmods = "sata";
+ reg = <0x4a141100 0x7>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dwc-ahci@4a140000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0x4a140000 0x1100>;
+ interrupts = <0 54 0x4>;
+ phys = <&sata_phy>;
+ phy-names = "sata-phy";
+ clocks = <&sata_ref_clk>;
+ clock-names = "optclk";
+ };
+ };
+
+
mcspi1: spi@48098000 {
compatible = "ti,omap4-mcspi";
reg = <0x48098000 0x200>;
--
1.7.4.1
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