On 07/23/2013 02:20 AM, Tero Kristo wrote:
This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.
Signed-off-by: Tero Kristo <t-kristo@xxxxxx>
---
arch/arm/boot/dts/omap443x-clocks.dtsi | 17 +
arch/arm/boot/dts/omap443x.dtsi | 8 +
arch/arm/boot/dts/omap4460.dtsi | 8 +
arch/arm/boot/dts/omap446x-clocks.dtsi | 27 +
arch/arm/boot/dts/omap44xx-clocks.dtsi | 1654 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/omap44xx-common-clocks.dtsi ?
5 files changed, 1714 insertions(+)
create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 0000000..2bd82b2
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Device Tree Source for OMAP443x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
Doing
/include/ "omap44xx-clocks.dtsi" might avoid including that header in
corresponding SoC dtsi,
OR:
+bandgap_fclk: bandgap_fclk@4a307888 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
+ bit-shift = <8>;
+ reg = <0x4a307888 0x4>;
+};
Since we already have omap443x.dtsi and omap446x.dtsi, do we need
clock.dtsi containing just a few entries?
instead we could define the delta clocks in the clocks section, and save
on two additional files, no?
[...]
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 0000000..ed6bc9b
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
[...]
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,autoidle-shift = <8>;
+ reg = <0x4a0041f0 0x4>;
+ bit-mask = <0x1f>;
+ index-starts-at-one;
+ ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+};
+
+abe_clk: abe_clk@4a004108 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x4a004108 0x4>;
+ bit-mask = <0x3>;
+ index-power-of-two;
+};
+
+aess_fclk: aess_fclk@4a004528 {
is there a naming convention used here? abe_clk, fclk etc?
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&abe_clk>;
+ bit-shift = <24>;
+ reg = <0x4a004528 0x4>;
+ bit-mask = <0x1>;
+};
[...]
+
+ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@4a0093e0 {
_ck?
[...]
--
Regards,
Nishanth Menon
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