Re: [alsa-devel] Query on Audio DMA using DMAEngine

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On 07/03/2013 01:12 PM, Mark Brown wrote:> On Wed, Jul 03, 2013 at 12:55:36PM
-0500, Joel Fernandes wrote:
>
>> When would it not be possible to cope with a large period size? Are there any
>> guidelines on what to consider when fixing a period size?
>
> This is an application issue not a driver issue.  An application that
> wants low latency may need high resolution information about what
> exactly the hardware is doing.
>

Hi Darren,

  Can anyone in your team share some insight about min/max buffer size and
min/max period size in the davinci-pcm driver. This will help make better
decisions about the Cyclic DMA. Below was my original email on the mailing list.

Also could you copy Peter? I couldn't find his email address.

Thanks,
Joel


Quoting my original email to the mailing list:


Copying some more lists are we're also discussing the DMA controller in the
SoCs. Thanks.

On 07/03/2013 04:43 AM, Mark Brown wrote:
> On Wed, Jul 03, 2013 at 11:09:22AM +0200, Lars-Peter Clausen wrote:
>> On 07/02/2013 02:13 PM, Mark Brown wrote:
>
>>> This sort of cyclic thing tends to be best, ideally you don't need
>>> interrupts at all (other than a timer).
>
>> Yes, this is usually how it is done. But I'm wondering maybe the EDMA
>> controller only has a small total amount of slots available.
>
> Well, you don't need particularly many slots so long as you can cope
> with a large period size.

Hi Mark,

When would it not be possible to cope with a large period size? Are there any
guidelines on what to consider when fixing a period size?

I see tegra and aux1x go upto .period_bytes_min = 1024

About slots, following are no.of slots on some SoCs with EDMA:

am1808 - 96 slots available + 32 taken up for channel but can be reused with
some changes.
am335x - 172 slots available + 64 taken up for channels

On a slightly different note, about buffer_bytes_max, is there any drawback to
setting it to a smaller value? Currently 128K is about what is used on davinci-pcm.
My idea is to map to do the direct mapping to IRAM if the IRAM transfers are
really what are preventing the under runs, but 128K will be too much for the
buffer as we don't have that much IRAM infact it is just the boundary on am33xx
(128K)


Thanks,

-Joel


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