On Thu, 28 Mar 2013, Rajendra Nayak wrote: > omap3_noncore_dpll_set_rate() attempts an enable of bypass clk as well > as ref clk for every .set_rate attempt on a noncore DPLL, regardless of > whether the .set_rate results in the DPLL being locked or put in bypass. > Early at boot, while some of these DPLLs are programmed and locked > (using .set_rate for the DPLL), this causes an ordering issue. > > For instance, on OMAP5, the USB DPLL derives its bypass clk from ABE DPLL. > If a .set_rate of USB DPLL which programmes the M,N and locks it is called > before the one for ABE, the enable of USB bypass clk (derived from ABE DPLL) > then attempts to lock the ABE DPLL and fails as the M,N values for ABE > are yet to be programmed. > > To get rid of this ordering needs, enable bypass clk for a DPLL as part > of its .set_rate only when its being put in bypass, and only enable the > ref clk when its locked. > > Reported-by: Roger Quadros <rogerq@xxxxxx> > Signed-off-by: Rajendra Nayak <rnayak@xxxxxx> Thanks, queued for 3.10. - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
