From: Ambresh K <ambresh@xxxxxx> Program the power management shadow register on freq update Else the concept of threshold frequencies dont really matter as the system always uses the performance mode timing for LP which is programmed in at init time. Signed-off-by: Nishanth Menon <nm@xxxxxx> Signed-off-by: Ambresh K <ambresh@xxxxxx> Signed-off-by: Lokesh Vutla <lokeshvutla@xxxxxx> --- drivers/memory/emif.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c index 622638c..16f5089 100644 --- a/drivers/memory/emif.c +++ b/drivers/memory/emif.c @@ -815,6 +815,8 @@ static void setup_registers(struct emif_data *emif, struct emif_regs *regs) writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW); writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW); + writel(regs->pwr_mgmt_ctrl_shdw, + base + EMIF_POWER_MANAGEMENT_CTRL_SHDW); /* Settings specific for EMIF4D5 */ if (emif->plat_data->ip_rev != EMIF_4D5) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
