On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index ee8a1e4..bcd2efb 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -56,6 +56,7 @@
#include "omap4-sar-layout.h"
#include "pm.h"
#include "prcm_mpu44xx.h"
+#include "prcm_mpu54xx.h"
#include "prminst44xx.h"
#include "prcm44xx.h"
#include "prm44xx.h"
@@ -83,6 +84,7 @@ extern void omap4_cpu_resume(void);
static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
static struct powerdomain *mpuss_pd;
static void __iomem *sar_base;
+static u32 cpu_context_offset;
static int default_finish_suspend(unsigned long cpu_state)
{
@@ -186,14 +188,14 @@ static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
if (cpu_id) {
reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
- OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+ cpu_context_offset);
omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
- OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+ cpu_context_offset);
} else {
reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
- OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+ cpu_context_offset);
omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
- OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+ cpu_context_offset);
}
}
@@ -431,6 +433,9 @@ int __init omap4_mpuss_init(void)
omap_pm_ops.finish_suspend = omap4_finish_suspend;
omap_pm_ops.resume = omap4_cpu_resume;
omap_pm_ops.scu_prepare = scu_pwrst_prepare;
+ cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
+ } else if (soc_is_omap54xx()) {
+ cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
}
return 0;
--
1.7.9.5
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