It seems to me that this capebus discussion is missing an important point. The name capebus suggests that it is a bus, so there should be a parent node to represent that bus. It should have a driver whose API implements all of the system-interface functions a cape needs. If you look at the way that interrupt specifiers work, the default case is that a child device implicitly delegates the mapping to its parent. The use of phandles to break out of the tree structure was intended for use within the "hardwired motherboard domain", not for plug-in devices. The "new" phandle-based GPIO and clock mechanisms don't have that parent-delegation feature, but they should, because hierarchical hardware is a good thing when it exists. One fix would be to designate a reserved phandle value - for example 0 or -1 - to mean "my parent". t The parent node would contain some translator to resolve the actual target node, similarly to interrupts and addresses. If done correctly, capebus "overlays" would then just be proper child nodes of the capebus bus node and there would no need to refer to "global" information like non-parent phandles. If something about the design of capebus makes that impossible, I respectfully suggest that its design should be reviewed, taking into account the many years of industry experience about modularity. Mitch -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
