Hi
On Thu, 19 Jul 2012, Tero Kristo wrote:
> On OMAP4430 HS / EMU chips, ROM code appears to re-configure L4PER domain
> next powerstate during wakeup from OSWR / OFF, programming it to ON.
> This will prevent successive entries to cpuidle retention / off, until
> kernel decices to change the L4PER target state, which can be delayed
> for a very long time as kernel is lazy programming the target state.
>
> This patch fixes the issue within the low power OSWR / OFF mode code, so
> that this register is saved / restored across MPU OSWR / OFF state.
>
> This problem seems to only occur with OMAP4430 HS/EMU, it does not impact
> OMAP4460+ or GP devices.
>
> Signed-off-by: Tero Kristo <t-kristo@xxxxxx>
> ---
> arch/arm/mach-omap2/omap-mpuss-lowpower.c | 39 ++++++++++++++++++++++++++++-
> arch/arm/mach-omap2/pm.h | 1 +
> arch/arm/mach-omap2/pm44xx.c | 10 +++++++
> 3 files changed, 49 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
> index 0e5f81b..963a61b 100644
> --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
> +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
...
> @@ -215,6 +225,28 @@ static void save_l2x0_context(void)
> {}
> #endif
>
> +static inline void save_l4per_regs(void)
> +{
> + int i;
> +
> + if (!IS_PM44XX_ERRATUM(PM_OMAP4_ROM_L4PER_ERRATUM_PWSTCT))
> + return;
> +
> + for (i = 0; i < ARRAY_SIZE(l4per_reg); i++)
> + l4per_reg[i].val = __raw_readl(l4per_reg[i].addr);
This is accessing the system PRM registers directly. We're trying to
remove these raw register accesses from non-PRM code because a PRM driver
is in the works. Please move this to prm44xx.c or prminst44xx.c and
implement a higher-level interface that omap-mpuss-lowpower.c can call.
- Paul
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
