"Shilimkar, Santosh" <santosh.shilimkar@xxxxxx> writes: > On Thu, May 17, 2012 at 10:45 PM, Kevin Hilman <khilman@xxxxxx> wrote: [...] >> What's not at all clear is what the ROM code does *after* this. Does it >> clear both bits? or just bit 0? Since it's r1pX based, I would expect >> that it doesn't touch anything other than bit 0. >> > Actually since the condition of control register == 1 is not satisfied, > It re-inits entire GIC thinking it's not configured at all. So everything > will be cleared and including non-secure GIC dist. enable bit. Aha, that's the missing piece of the puzzle: The ROM code is clearing bits that are unused on r1pX (but used on r2pX). That is the root of this bug and needs more description. Thanks for clarifying. [...] >> Santosh, I do understand what is happening here. But I play dumb so >> that it will be described in great detail in the changelog so that when >> I forget (and you forget) we can go back to this and get a quick >> understanding of both the bug and the workaround. >> >> Since you are very deeply familiar with this bug, it's understandably >> hard to write this changelog since most things probably seem obvious to >> you. A suggestion would be to have a few colleagues that are not >> familiar with this bug read the changelog and try and describe it back >> to you. >> > I agree with you. This is side effect of knowing some BUGs too much. > I will work with Tero so that change log captures more details. Thanks. Maybe Jon Hunter can help review the changelog too. IMO, he is the reigning champion of thorough, descriptive and detailed changelogs. :) Kevin -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
