Any update on this?
On Thu, Jan 19, 2012 at 11:22 AM, Ameya Palande <ameya.palande@xxxxxx> wrote:
> From: Rajendra Nayak <rnayak@xxxxxx>
>
> All DPLLs except USB are in ALWON powerdomain. Make sure the
> clkdm/pwrdm for USB DPLL (l3init) is turned on before attempting
> a DPLL relock. So, mark the database accordingly.
>
> Without this fix, it was seen that DPLL relock fails while testing
> relock in a loop of USB DPLL.
>
> CC: Nishanth Menon <nm@xxxxxx>
> Tested-by: Ameya Palande <ameya.palande@xxxxxx>
> Signed-off-by: Rajendra Nayak <rnayak@xxxxxx>
> ---
> arch/arm/mach-omap2/clock44xx_data.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
> index 08e86d7..9519374 100644
> --- a/arch/arm/mach-omap2/clock44xx_data.c
> +++ b/arch/arm/mach-omap2/clock44xx_data.c
> @@ -974,6 +974,7 @@ static struct clk dpll_usb_ck = {
> .recalc = &omap3_dpll_recalc,
> .round_rate = &omap2_dpll_round_rate,
> .set_rate = &omap3_noncore_dpll_set_rate,
> + .clkdm_name = "l3_init_clkdm",
> };
>
> static struct clk dpll_usb_clkdcoldo_ck = {
> --
> 1.7.4.1
>
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