From: Paul Walmsley <paul@xxxxxxxxx>
Sometimes, the automatic voltage scaling control loop parameters in
the SoC eFuse data are not present or are incorrect. Nevertheless,
some boards may wish to use SmartReflex anyway, with conservative
values provided by the SoC manufacturer. This patch adds code to
allow board files to specify or override the SmartReflex eFuse data.
Signed-off-by: Paul Walmsley <paul@xxxxxxxxx>
Signed-off-by: Jean Pihet <j-pihet@xxxxxx>
Cc: Thara Gopinath <thara@xxxxxx>
Cc: Nishanth Menon <nm@xxxxxx>
Cc: Kevin Hilman <khilman@xxxxxx>
---
arch/arm/mach-omap2/sr_device.c | 40 ++++++++++++++++++++++----------------
arch/arm/mach-omap2/voltage.h | 2 +
2 files changed, 25 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 8fe836f..2dec827 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -7,8 +7,9 @@
* Copyright (C) 2010 Texas Instruments, Inc.
* Thara Gopinath <thara@xxxxxx>
*
- * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2008, 2011 Nokia Corporation
* Kalle Jokiniemi
+ * Paul Walmsley
*
* Copyright (C) 2007 Texas Instruments, Inc.
* Lesly A M <x0080970@xxxxxx>
@@ -54,31 +55,36 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
for (i = 0, j = 0; i < count; i++) {
u32 v;
- /*
- * In OMAP4 the efuse registers are 24 bit aligned.
- * A __raw_readl will fail for non-32 bit aligned address
- * and hence the 8-bit read and shift.
- */
- if (cpu_is_omap44xx()) {
- u16 offset = volt_data[i].sr_efuse_offs;
-
- v = omap_ctrl_readb(offset) |
- omap_ctrl_readb(offset + 1) << 8 |
- omap_ctrl_readb(offset + 2) << 16;
+ if (volt_data[i].sr_nvalue != 0) {
+ v = volt_data[i].sr_nvalue;
} else {
- v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+ /*
+ * In OMAP4 the efuse registers are 24 bit
+ * aligned. A __raw_readl will fail for
+ * non-32 bit aligned address and hence the
+ * 8-bit read and shift.
+ */
+ if (cpu_is_omap44xx()) {
+ u16 offset = volt_data[i].sr_efuse_offs;
+
+ v = omap_ctrl_readb(offset) |
+ omap_ctrl_readb(offset + 1) << 8 |
+ omap_ctrl_readb(offset + 2) << 16;
+ } else {
+ v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+ }
}
/*
* Many OMAP SoCs don't have the eFuse values set.
* For example, pretty much all OMAP3xxx before
* ES3.something.
- *
- * XXX There needs to be some way for board files or
- * userspace to add these in.
*/
- if (v == 0)
+ if (v == 0) {
+ pr_debug("SR: %s: voltage %d: no N value; skipping\n",
+ sr_data->voltdm->name, volt_data[i].volt_nominal);
continue;
+ }
nvalue_table[j].nvalue = v;
nvalue_table[j].errminlimit = volt_data[i].sr_errminlimit;
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 16a1b09..ebd8899 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -96,6 +96,7 @@ struct voltagedomain {
* @sr_efuse_offs: The offset of the efuse register(from system
* control module base address) from where to read
* the n-target value for the smartreflex module.
+ * @sr_nvalue: the SR N value for this OPP. Use to override bogus eFuse vals
* @sr_errminlimit: Error min limit value for smartreflex. This value
* differs at differnet opp and thus is linked
* with voltage.
@@ -105,6 +106,7 @@ struct voltagedomain {
struct omap_volt_data {
u32 volt_nominal;
u32 sr_efuse_offs;
+ u32 sr_nvalue;
u8 sr_errminlimit;
u8 vp_errgain;
};
--
1.7.5.4
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