Hi,
On Thu, 10 Nov 2011, Tony Lindgren wrote:
* Aaro Koskinen <aaro.koskinen@xxxxxx> [111110 13:31]:
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -774,14 +774,6 @@ int __init omap1_clk_init(void)
int crystal_type = 0; /* Default 12 MHz */
u32 reg, cpu_mask;
-#ifdef CONFIG_DEBUG_LL
- /*
- * Resets some clocks that may be left on from bootloader,
- * but leaves serial clocks on.
- */
- omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
-#endif
-
/* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
omap_writew(reg, SOFT_REQ_REG);
Hmm that should keep the serial clocks on. What other bit(s) need to
be on in MOD_CONF_CTRL_0 for you in addition to the serial bits?
On my board those serial bits are zero during the early boot (and the
serial works). By setting those bits the clock will switch from 12 ->
48 MHz and I guess the baud rate will change and that's why the output
turns into garbage.
So I think the code should reset the other bits, and leave serial bits
untouched:
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 1297bb5..b3b69d8 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -788,7 +788,11 @@ int __init omap1_clk_init(void)
* Resets some clocks that may be left on from bootloader,
* but leaves serial clocks on.
*/
- omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
+ reg = omap_readl(MOD_CONF_CTRL_0) &
+ ((1 << CONF_MOD_UART1_CLK_MODE_R) |
+ (1 << CONF_MOD_UART2_CLK_MODE_R) |
+ (1 << CONF_MOD_UART3_CLK_MODE_R));
+ omap_writel(reg, MOD_CONF_CTRL_0);
#endif
/* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
A.
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