OMAP HSMMC data timeout calculation

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Hi all,


I am trying to understand data timeout value (dto) calculation done in omap hsmmc driver (omap_hsmmc.c)

I summed my understanding & my doubts in below code [GH].

Can someone help me in understanding the code


Thanks in advance.

Regards
Gururaja

static void set_data_timeout(struct omap_hsmmc_host *host,
			     unsigned int timeout_ns,
			     unsigned int timeout_clks)
{
	unsigned int timeout, cycle_ns;
	uint32_t reg, clkd, dto = 0;

	reg = OMAP_HSMMC_READ(host->base, SYSCTL);
	clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
	if (clkd == 0)
		clkd = 1;

	cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
	timeout = timeout_ns / cycle_ns;
	timeout += timeout_clks;

[GH] till here, data time out calculation for the card is calclated in terms of host controller clock rate


	if (timeout) {
		while ((timeout & 0x80000000) == 0) {
			dto += 1;
			timeout <<= 1;
		}
		dto = 31 - dto;

[GH] what is achieved here?


		timeout <<= 1;
		if (timeout && dto)
			dto += 1;

[GH] what is achieved here?


		if (dto >= 13)
			dto -= 13;
		else
			dto = 0;

[GH] why is 13 subtracted when the value is >13 & if <13, why is it made 0


		if (dto > 14)
			dto = 14;

[GH] This is done to limit the max value.

	}


	reg &= ~DTO_MASK;
	reg |= dto << DTO_SHIFT;
	OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
}


Regards
Gururaja
��.n��������+%������w��{.n�����{�������ܨ}���Ơz�j:+v�����w����ޙ��&�)ߡ�a����z�ޗ���ݢj��w�f



[Index of Archives]     [Linux Arm (vger)]     [ARM Kernel]     [ARM MSM]     [Linux Tegra]     [Linux WPAN Networking]     [Linux Wireless Networking]     [Maemo Users]     [Linux USB Devel]     [Video for Linux]     [Linux Audio Users]     [Yosemite Trails]     [Linux Kernel]     [Linux SCSI]

  Powered by Linux