Re: [PATCH 7/8] OMAP3: update cpuidle latency and threshold figures

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Hi Ming,

On Wed, Oct 12, 2011 at 4:48 AM, Ming Lei <tom.leiming@xxxxxxxxx> wrote:
> Hi,
>
> On Thu, Sep 22, 2011 at 12:14 AM, Jean Pihet <jean.pihet@xxxxxxxxxxxxxx> wrote:
>> Update the data from the measurements performed at HW and SW levels.
>>
>> Cf. http://www.omappedia.org/wiki/Power_Management_Device_Latencies_Measurement
>> for a detailed explanation on where are the numbers magically coming from.
>>
>> ToDo:
>> - Measure the wake-up latencies for all power domains for OMAP3
>> - Correct some numbers when sys_clkreq and sys_offmode are supported
>>
>> Signed-off-by: Jean Pihet <j-pihet@xxxxxx>
>> ---
>>  arch/arm/mach-omap2/cpuidle34xx.c |   28 ++++++++++++++--------------
>>  1 files changed, 14 insertions(+), 14 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
>> index 1b8e0da..4b3e994 100644
>> --- a/arch/arm/mach-omap2/cpuidle34xx.c
>> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
>> @@ -44,20 +44,20 @@
>>  * pass these details from the board file.
>>  */
>>  static struct cpuidle_params cpuidle_params_table[] = {
>> -       /* C1 */
>> -       {2 + 2, 5, 1},
>> -       /* C2 */
>> -       {10 + 10, 30, 1},
>> -       /* C3 */
>> -       {50 + 50, 300, 1},
>> -       /* C4 */
>> -       {1500 + 1800, 4000, 1},
>> -       /* C5 */
>> -       {2500 + 7500, 12000, 1},
>> -       /* C6 */
>> -       {3000 + 8500, 15000, 1},
>> -       /* C7 */
>> -       {10000 + 30000, 300000, 1},
>> +       /* C1 . MPU WFI + Core active */
>> +       {73 + 78, 152, 1},
>> +       /* C2 . MPU WFI + Core inactive */
>> +       {165 + 88, 345, 1},
>> +       /* C3 . MPU CSWR + Core inactive */
>> +       {163 + 182, 345, 1},
>> +       /* C4 . MPU OFF + Core inactive */
>> +       {2852 + 605, 150000, 1},
>> +       /* C5 . MPU RET + Core RET */
>> +       {800 + 366, 2120, 1},
>
> C4 exit_latency is longer than C5's, not sure if it is correct?
Since MPU is OFF in C4 the impact is bigger in latency. In MPU OFF
mode the caches and MPU context are saved and later restored, which is
costly.

Thanks for the review!

Regards,
Jean

>
>> +       /* C6 . MPU OFF + Core RET */
>> +       {4080 + 801, 215000, 1},
>> +       /* C7 . MPU OFF + Core OFF */
>> +       {4300 + 13000, 215000, 1},
>>  };
>>  #define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
>>
>> --
>> 1.7.4.1
>>
>> --
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>
>
> thanks,
> --
> Ming Lei
>
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