Hi Jean On Wed, 21 Sep 2011, jean.pihet@xxxxxxxxxxxxxx wrote: > From: Jean Pihet <j-pihet@xxxxxx> > > Figures are added to the power domains structs for RET and OFF modes. > > Note: the latency figures for MPU, PER, CORE, NEON have been obtained > from actual measurements. > The latency figures for the other power domains are preliminary and > shall be added. > > Cf. http://www.omappedia.org/wiki/Power_Management_Device_Latencies_Measurement > for a detailed explanation on where are the numbers magically coming from. > > Tested on OMAP3 Beagleboard in RET/OFF using wake-up latency constraints > on MPU, CORE and PER. Do the CSWR measurements include the time for the PMIC to scale the voltage, or do they just represent the time to enter and exit clock stop (presumably with DPLL idling)? - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
