From: Gulati, Shweta <shweta.gulati@xxxxxx>
Core Clk Tree shows incorrect Clk rates at OPP50, as
in commit e07f469d284ca3d1f5dcf5438c22982be98bc071
calling of 'recalc' in API clk_set_rate is unintentionally
removed, because of which clock's tree rates get goofed
up when DVFS happens. This Patch adds recalc API back.
Tested on OMAP3630 SDP Board.
Signed-off-by: Shweta Gulati <shweta.gulati@xxxxxx>
Cc: Rajendra Nayak <rnayak@xxxxxx>
Cc: Paul Wamsley <paul@xxxxxxxxx>
---
arch/arm/plat-omap/clock.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index c9122dd..5a0d06b 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -130,8 +130,11 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
spin_lock_irqsave(&clockfw_lock, flags);
ret = arch_clock->clk_set_rate(clk, rate);
- if (ret == 0)
+ if (ret == 0) {
+ if (clk->recalc)
+ clk->rate = clk->recalc(clk);
propagate_rate(clk);
+ }
spin_unlock_irqrestore(&clockfw_lock, flags);
return ret;
--
1.7.0.4
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