On Mon, 2011-04-11 at 12:20 -0600, Paul Walmsley wrote: > Hi > > On Mon, 11 Apr 2011, Tomi Valkeinen wrote: > > However, I think there is one difference between the clock used just to > > enable the DSS registers, and the one used to output pixels: we need to > > be able to adjust the rate of the clock. Thus we need to have a common > > (omap2/3/4) clock name for it to be able to clk_get() it. > > > > Should that clock name be just the "main" clock provided automatically, > > or something else? > > Are you referring here to the system DPLL and its output dividers, or are > you referring to the DSS module's internal dividers? The system DPLL and its divider. If we are using the dss_dss_clk as fclk, we need to adjust it depending on the required pixel clock and use cases (e.g. some scaling factors may need higher fclk). Tomi -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
