"Avinash.H.M" <avinashhm@xxxxxx> writes:
> The i2c module has a special reset sequence. The sequence is
> - Disable the I2C.
> - Write to SOFTRESET bit.
> - Enable the I2C.
> - Poll on the RESETDONE bit.
> This sequence must be followed for i2c reset in omap2, omap3. The sequence is
> implemented as a function and the i2c_class is updated with the correct
> 'reset' pointer.
>
> Cc: Rajendra Nayak <rnayak@xxxxxx>
> Cc: Paul Walmsley <paul@xxxxxxxxx>
> Cc: Benoit Cousson <b-cousson@xxxxxx>
> Cc: Kevin Hilman <khilman@xxxxxx>
> Signed-off-by: Avinash.H.M <avinashhm@xxxxxx>
[...]
> +
> +/**
> + * omap_i2c_reset- reset the omap i2c module.
> + * @oh: struct omap_hwmod *
> + *
> + * The i2c moudle in omap2, omap3 had a special sequence to reset. The
> + * sequence is:
> + * - Disable the I2C.
> + * - Write to SOFTRESET bit.
> + * - Enable the I2C.
> + * - Poll on the RESETDONE bit.
> + * The sequence is implemented in below function. This is called for 2420,
> + * 2430 and omap3.
> + */
> +int omap_i2c_reset(struct omap_hwmod *oh)
> +{
> + u32 v;
> + int c = 0;
> +
> + /* Disable I2C */
> + v = omap_hwmod_read(oh, I2C_CON_OFFSET);
> + v = v & ~I2C_EN;
> + omap_hwmod_write(v, oh, I2C_CON_OFFSET);
> +
> + /* Write to the SOFTRESET bit */
> + v = oh->_sysc_cache;
> + v |= (0x1 << oh->class->sysc->sysc_fields->srst_shift);
> +
> + oh->_sysc_cache = v;
> + omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
Direct SYSCONFIG access isn't right here. This should go through
omap_hwmod.
What is probably needed is exposing _ocp_softreset to device code
via something like omap_hwmod_ocp_softreset() and calling that here.
Kevin
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