On 5 December 2010 11:43, Russell King - ARM Linux
<linux@xxxxxxxxxxxxxxxx> wrote:
> As our SMP implementation uses MESI protocols. ÂGrouping together data
> which is mostly only read together means that we avoid unnecessary
> cache line bouncing when this code shares a cache line with other data.
>
> In other words, cache lines associated with read-mostly data are
> expected to spend most of their time in shared state.
>
> Signed-off-by: Russell King <rmk+kernel@xxxxxxxxxxxxxxxx>
> ---
> Âarch/arm/include/asm/cache.h Â| Â Â2 ++
> Âarch/arm/kernel/vmlinux.lds.S | Â Â1 +
> Â2 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
> index 9d61220..75fe66b 100644
> --- a/arch/arm/include/asm/cache.h
> +++ b/arch/arm/include/asm/cache.h
> @@ -23,4 +23,6 @@
> Â#define ARCH_SLAB_MINALIGN 8
> Â#endif
>
> +#define __read_mostly __attribute__((__section__(".data..read_mostly")))
> +
> Â#endif
> diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
> index cead889..1581f6d 100644
> --- a/arch/arm/kernel/vmlinux.lds.S
> +++ b/arch/arm/kernel/vmlinux.lds.S
> @@ -167,6 +167,7 @@ SECTIONS
>
> Â Â Â Â Â Â Â ÂNOSAVE_DATA
> Â Â Â Â Â Â Â ÂCACHELINE_ALIGNED_DATA(32)
> + Â Â Â Â Â Â Â READ_MOSTLY_DATA(32)
Should we change the alignments to 64?
--
Catalin
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