On Wed, Nov 24, 2010 at 05:51:50PM +0100, ext Sripathy, Vishwanath wrote: > Nishant, > > On Fri, Nov 19, 2010 at 7:24 AM, Nishanth Menon <nm@xxxxxx> wrote: > > From: Peter 'p2' De Schrijver <peter.de-schrijver@xxxxxxxxx> > > > > Errata i581 impacts OMAP3 platforms. > > PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing > > the DPLL not to be locked at times. > > > > IMPORTANT: this is not a complete workaround implementation as recommended > > by the silicon errata. this is a support logic for detecting lockups and > > attempting to recover where possible and is known to provide stability > > in multiple platforms. > > How does this WA work when Core enters off mode? SRAM contents are > lost when Core enters off. So how this code is copied to SRAM upon > wakeup? Where is this code placed when Core entered off mode? > This code is mostly important for inactive and retention. The ROM code waits for the maximum dll lock time when resuming from off mode. So for off mode this code isn't really needed. Cheers, Peter. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
