Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote: > On Mon, 2010-10-18 at 14:35 +0100, Russell King - ARM Linux wrote: >> In any case, Linux's spinlock API (or more accurately, the ARM exclusive >> access instructions) relies upon hardware coherency support (a piece of >> hardware called an exclusive monitor) which isn't present on the M3 nor >> DSP processors. So there's no way to ensure that updates from the M3 >> and DSP are atomic wrt the A9 updates. > > Right, so the problem is that there simply is no way to do atomic memory > access from these auxiliary processing units wrt the main CPU? Seeing as > they operate on the same memory space, wouldn't it make sense to have > them cache-coherent and thus provide atomicy guarantees through that? With cache coherency you may get atomicity of writes or reads but usually not atomic modifications. -- Catalin -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
