Re: [PATCH] omap3: Prevent SDRC deadlock when L3 is changing frequency

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Jon,

one other brief note:

On Wed, 21 Jul 2010, Jon Hunter wrote:

> diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
> index de99ba2..e87e730 100644
> --- a/arch/arm/mach-omap2/sram34xx.S
> +++ b/arch/arm/mach-omap2/sram34xx.S
> @@ -129,8 +129,11 @@ ENTRY(omap3_sram_configure_core_dpll)
>  	ldr	r4, [sp, #80]
>  	str     r4, omap_sdrc_mr_1_val
>  skip_cs1_params:
> +	mrc p15, 0, r8, c1, c0, 0	@ read aux ctrl register
> +	bic r10, r8, #0x800		@ clear Z-bit, disable branch prediction
> +	mcr p15, 0, r10, c1, c0, 0	@ write aux ctrl register

Please be careful with the whitespace between the opcode and the 
arguments - I will fix this in the current patch but it seems best to keep 
this consistent.


- Paul
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