Hi, I'm trying to transfer from an FPGA peripheral on the 3530's GPMC bus to external RAM on a 2.6.32 kernel. Transferring words using *ram_buffer = __raw_readw(peripheral_addr) works for non-DMA copies and I've checked that the DMA cycle works in my driver by using another location in RAM as the source instead of the peripheral register and I get values and an interrupt as expected, but when using the FPGA as source all values are 0xff. The FPGA uses WAIT1 to signal read/write completion and I've set GPMC_CONFIG6_CYCLE2CYCLEDELAY so chip select is toggled between transfers as the FPGA hardware currently requires. Does a DMA transfer use GPMC settings for timing? Are there other settings I need to worry about for this case? Thanks! , John -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
