Sergio > -----Original Message----- > From: Aguirre, Sergio > Sent: Friday, August 20, 2010 5:09 PM > To: Kanigeri, Hari; Hiroshi Doyu; Linux omap > Subject: RE: [PATCH] omap:iommu-load cam register before flushing the > entry > > Hi Hari, > > > -----Original Message----- > > From: linux-omap-owner@xxxxxxxxxxxxxxx [mailto:linux-omap- > > owner@xxxxxxxxxxxxxxx] On Behalf Of Kanigeri, Hari > > Sent: Friday, August 20, 2010 8:50 AM > > To: Hiroshi Doyu; Linux omap > > Cc: Kanigeri, Hari > > Subject: [PATCH] omap:iommu-load cam register before flushing the entry > > > > The flush_iotlb_page is not loading the cam register before flushing > > the cam entry. This causes wrong entry to be flushed out from the TLB, > and > > if the entry happens to be a locked TLB entry it would lead to MMU > faults. > > > > The fix is to load the cam register with the address to be flushed > before > > flushing the TLB entry. > > I'm curious... does this impact OMAP3 ISP aswell? Or is it for OMAP4 only? > This is valid for OMAP3 as well. > Regards, > Sergio > > > > > Signed-off-by: Hari Kanigeri <h-kanigeri2@xxxxxx> > > --- > > arch/arm/plat-omap/iommu.c | 1 + > > 1 files changed, 1 insertions(+), 0 deletions(-) > > > > diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c > > index 2e603fe..c534280 100644 > > --- a/arch/arm/plat-omap/iommu.c > > +++ b/arch/arm/plat-omap/iommu.c > > @@ -315,6 +315,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da) > > if ((start <= da) && (da < start + bytes)) { > > dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", > > __func__, start, da, bytes); > > + iotlb_load_cr(obj, &cr); > > iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); > > } > > } > > -- > > 1.7.0 > > > > Thank you, Best regards, Hari -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
