Tony Lindgren had written, on 07/06/2010 08:14 AM, the following:
* Nishanth Menon <nm@xxxxxx> [100706 15:47]:
On 07/06/2010 07:46 AM, Tony Lindgren wrote:
* Nishanth Menon<nm@xxxxxx> [100623 05:10]:
add a minimalist feature - l2cache for omap1.
Signed-off-by: Nishanth Menon<nm@xxxxxx>
---
arch/arm/mach-omap1/id.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index 91dbb71..b98a17f 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -200,5 +200,11 @@ void __init omap1_check_revision(void)
printk(KERN_INFO " revision %i handled as %02xxx id: %08x%08x\n",
die_rev, omap_revision& 0xff, system_serial_low,
system_serial_high);
+
+ /*
+ * TODO: add a better check feature once we have
+ * more decent feature check
+ */
+ omap_features |= OMAP_HAS_L2CACHE;
}
There's no L2 cache on omap1?
I thought it did, hence added.. am I wrong?
Maybe you're thinking something else.. But for example, 1710 TRM says:
ARM926EJ
L1 32K-byte, four-way set-associative instruction cache
L1 16K-byte, four-way set-associative data cache with write buffer
Then 2430 TRM says:
ARM1136JF-S
32K-byte instructions and 32K-byte data--4-way associative
64-entry instruction and 64-entry data memory management units (MMUs)
So no L2 until 34xx I believe.
Regards,
Tony
Arrgh.. my bad. you are right.
here is a bigger list I just checked internally with TRMs
1510 - TI925T - no L2.
A separate 16K-byte instruction cache and 8K-byte data cache. Both are
two-way associative with virtual index virtual tag (VIVT)
1610 - ARM926EJ
L1 16K-byte, four-way set-associative instruction cache
L1 8K-byte, four-way set-associative data cache with write buffer
1710 - ARM926EJ
L1 32K-byte, four-way set-associative instruction cache
L1 16K-byte, four-way set-associative data cache with write buffer
2420 (2.3) - ARM1136JF-S
– 32-KB instruction and 32-KB data; 4-way set associative memory
management units (MMUs)
– 64-entry instruction and 64-entry data write buffer
2430 (2.1) -
– 32K-byte instructions and 32K-byte data—4-way associative
– 64-entry instruction and 64-entry data memory management units (MMUs)
Please drop 9/9, and I will post a new revision of 8/9 without L2 enabled.
--
Regards,
Nishanth Menon
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