On Fri, Feb 19, 2010 at 10:03:32AM -0800, Tony Lindgren wrote:
> If so, then what have in arch/arm/plat-omap/iommu.c seems buggy:
>
> static void flush_iopgd_range(u32 *first, u32 *last)
> {
> /* FIXME: L2 cache should be taken care of if it exists */
> do {
> asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
> : : "r" (first));
> first += L1_CACHE_BYTES / sizeof(*first);
> } while (first <= last);
> }
>
> It seems that this code should use the real cache line size instead to
> avoid every other line not to flush if ARM_L1_CACHE_SHIFT is set larger
> than it is.
Yes.
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