Hi, On Wed, 10 Feb 2010, Vishwanath BS wrote: > In 3630, DPLL4M2 o/p can be 96MH or 192MHz (for SGX to run at 192). This > patch has changes to support this feature. 96MHz clock is generated by > dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register. > SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's > functional clock. In summary changes done are 1. Added a feature called > omap3_has_192mhz_clk and enabled for 3630 2. Added a new clock node > called omap_192m_alwon_ck 3. Made omap_96m_alwon_fck to derive it's > clock from omap_192m_alwon_ck > > Cc: Paul Walmsley <paul@xxxxxxxxx> > > Signed-off-by: Vishwanath BS <Vishwanath.bs@xxxxxx> this patch still had a whitespace problem, but I fixed it up here and queued it for 2.6.34. - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
