RE: [PATCHV3] OMAP3630: Clock: Workaround for DPLL HS divider limitation

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Thanks :)

> -----Original Message-----
> From: Paul Walmsley [mailto:paul@xxxxxxxxx]
> Sent: Wednesday, February 10, 2010 11:55 AM
> To: G.N, Vijayakumar
> Cc: linux-omap@xxxxxxxxxxxxxxx; Sripathy, Vishwanath; Turquette, Mike;
> khilman@xxxxxxxxxxxxxxxxxxx
> Subject: RE: [PATCHV3] OMAP3630: Clock: Workaround for DPLL HS divider
> limitation
> 
> Hello Vijayakumar,
> 
> On Wed, 10 Feb 2010, G.N, Vijayakumar wrote:
> 
> > > From: Paul Walmsley [mailto:paul@xxxxxxxxx]
> > >
> > > Shouldn't there also be a:
> > >
> > > dummy_v &= clk->parent->clksel_mask;
> > >
> > > here to avoid writing to reserved bits?
> >
> > XOR with "0x00" will always retains the original values, hence I don't see any
> requirement of mask.
> >
> > Example:
> > For CM_CLKSEL1_PLL
> >
> > clksel_mask:
> > #define OMAP3430_DIV_DPLL3_MASK				(0x1f <<
> 16)
> >
> > clksel_shift = __ffs(clk->parent->clksel_mask); becomes 16
> >
> > (1 << clksel_shift) will become (1 << 16)
> >
> > XOR operator will only change the Divisor's LSB 1st bit to it's negated value.
> >
> > Hence we will be always changing the Divisor's LSB 1's bit and hence
> >  the value written will be different one from the existing value and won't be
> touching any reserved fileds.
> 
> OK, thanks, looks like I misread the code.  Queued for 2.6.34.
> 
> 
> - Paul
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