Hi Paul, > -----Original Message----- > From: Paul Walmsley [mailto:paul@xxxxxxxxx] > Sent: Thursday, January 14, 2010 2:31 AM > To: Reddy, Teerth > Cc: linux-omap@xxxxxxxxxxxxxxx; tony@xxxxxxxxxxx; Kevin Hilman > Subject: Re: [PATCH] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR > stall in SDRC after a Warm-reset > > Hello Teerth, > > another question that just occurred to me. > > On Wed, 13 Jan 2010, Paul Walmsley wrote: > > > > @@ -147,10 +149,9 @@ void omap_prcm_arch_reset(char mode) > > > * cf. OMAP34xx TRM, Initialization / Software Booting > > > * Configuration. */ > > > omap_writel(l, OMAP343X_SCRATCHPAD + 4); > > > + omap3_warmreset(); > > Wouldn't this code need to enable interrupts before calling > omap3_sram_warmreset()? Seems like an interrupt could occur after the > SDRC has been placed into idle which could effectively hang the ARM. I agree with you. I ll add the changes to disable interrupts before going for a warm reset. > I wonder if this also needs to make sure that all the other system > initiators are mute before continuing, for the same reason cited in commit > 18862cbe47e37beba98f22c088fbe6fe029df889 ? I suppose that, for example, > if an interrupt occurs on the IVA2.2 or the DMA controller tries to access > the SDRC, it would hopefully only wedge those initiators and not the whole > chip? Do you think we need to take care of the system initiators if we are disabling all the interrupts before going for a warm reset? I think this doesn't seem to hold good here. Please let me know if you understanding is wrong. Regards Teerth -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
