[PATCHV2 0/2] OMAP3630: Clock: Workaround for DPLL HS divider limitation

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>From e5dddd99557dc73a581001b39d595cfacdc45ec2 Mon Sep 17 00:00:00 2001
From: Vijaykumar GN <vijaykumar.gn@xxxxxx>
Date: Tue, 12 Jan 2010 17:15:29 +0530
Subject: [PATCH 0/2] OMAP3630: Clock: Workaround for DPLL HS divider limitation

This series of patch implements a workaround for the DPLL HS divider limitation
in OMAP3630.

Without this workaround the divider value goes to its reset state after the
corresponding PWRDN bit is set from the CM_CLKEN_PLL  register.
The correct divider value can be restored by writing dummy value to the
register than what is in there, and then re-writing the desired value. 
HS Dividers impacted are
1. DPLL3_M3
2. DPLL4_M2
3. DPLL4_M3
4. DPLL4_M4
5. DPLL4_M5
6. DPLL4_M6

This patch series has dependency on Clock framework reorganization available at
http://patchwork.kernel.org/patch/73638/
http://patchwork.kernel.org/patch/73635/
http://patchwork.kernel.org/patch/73637/
http://patchwork.kernel.org/patch/73636/

V1: Initial Patch Series
V2: Incorporated comments

Mike Turquette (2):
  OMAP3630: Clock: add clksel_shift to struct clk
  OMAP3630: Clock: Fixing HSDivider Limitation

 arch/arm/mach-omap2/clock34xx.c         |   36 ++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/clock34xx.h         |    1 +
 arch/arm/mach-omap2/clock34xx_data.c    |   21 ++++++++++++++++++++
 arch/arm/plat-omap/include/plat/clock.h |    1 +
 4 files changed, 62 insertions(+), 0 deletions(-)

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