* Gabi Voiculescu <boy3dfx2@xxxxxxxxx> [091027 13:24]: > Hello. > > I am working on porting a piece of code that makes use of irq on top of the performance counters (PMN) present in the OMAP3530's > Cortex A8 MPU. > > This code is ported from an armv6 platform (arm1176 cpu). On the original platform (pb1176) the interrupt number into the IC was known from the > documentation (39). > > I am unable to find the interrupt number for the performance counters and can not believe the TI people left the line unconnected to the GIC when they build the OMAP3530. > > I have searched in the TI documentation: Interrupt table (starting on page 1074 in http://focus.ti.com/lit/ug/spruff6b/spruff6b.pdf ) for a suitable entry but did not find it. > > I have tried to program a counter overflow and unmask the first 4 IRQs in > the MPU in the hope that one of these is the PMU irq, again without > success. > > *********** > > Did anybody get into this documentation problem? > > Did he find a fix for it? > > Is there a PMN interrupt in the OMAP3530 IC Interrupt table? Please take a look at arch/arm/oprofile/op_model_v7.c. Also search the mailing lists regarding the Cortex bug on the performance counter interrupt, basically the interrupt stops happening after some usage. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
