On Fri, Oct 30, 2009 at 9:00 AM, HU TAO-TGHK48 <taohu@xxxxxxxxxxxx> wrote:
> From a36dac7ee6140ffa23f0adc024964aaf3e266e5f Mon Sep 17 00:00:00 2001
> From: Tao Hu <taohu@xxxxxxxxxxxx>
> Date: Thu, 29 Oct 2009 17:17:21 -0500
> Subject: [PATCH] Fix race condition in omap_request_dma()
>
> The bug could cause irq enable bit of one DMA channel is
> cleared unexpectedly when 2 (or more) drivers are calling
> omap_request_dma() simultaneously
>
> Signed-off-by: Fei Yang <AFY095@xxxxxxxxxxxx>
> Signed-off-by: Tao Hu <taohu@xxxxxxxxxxxx>
> ---
> arch/arm/plat-omap/dma.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
> index cd53b28..6895484 100755
> --- a/arch/arm/plat-omap/dma.c
> +++ b/arch/arm/plat-omap/dma.c
> @@ -749,11 +749,13 @@ int omap_request_dma(int dev_id, const char
> *dev_name,
> }
>
> if (cpu_class_is_omap2()) {
> + spin_lock_irqsave(&dma_chan_lock, flags);
> omap2_enable_irq_lch(free_ch);
> omap_enable_channel_irq(free_ch);
> /* Clear the CSR register and IRQ status register */
> dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
> dma_write(1 << free_ch, IRQSTATUS_L0);
> + spin_unlock_irqrestore(&dma_chan_lock, flags);
> }
Nice catch. I think the lock needs to be applied only for the global
registers which are changed using the read - update - write method.
The dma_write to per channel configuration registers need not be
locked.
Hence the lock is better placed "within" omap2_enable_irq_lch
function. That way, if it's reused, the locking would also be in
place.
Thank you !
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