Configure default DSCP to User Priority mapping registers as per: https://datatracker.ietf.org/doc/html/rfc8325#section-4.3 and https://datatracker.ietf.org/doc/html/rfc8622#section-11 Also update Priority to Thread maping to be compliant with IEEE802.1Q-2014. Priority Code Point (PCP) 2 is higher priority than PCP 0 (Best Effort). PCP 1 (Background) is lower priority than PCP 0 (Best Effort). Signed-off-by: Roger Quadros <rogerq@xxxxxxxxxx> --- Changes in v4: - Updated default DSCP to User Priority mapping as per https://datatracker.ietf.org/doc/html/rfc8325#section-4.3 and https://datatracker.ietf.org/doc/html/rfc8622#section-11 - Link to v3: https://lore.kernel.org/r/20241109-am65-cpsw-multi-rx-dscp-v3-0-1cfb76928490@xxxxxxxxxx Changes in v3: - Added Reviewed-by tag to patch 1 - Added macros for DSCP PRI field size and DSCP PRI per register - Drop unnecessary readl() in am65_cpsw_port_set_dscp_map() - Link to v2: https://lore.kernel.org/r/20241107-am65-cpsw-multi-rx-dscp-v2-0-9e9cd1920035@xxxxxxxxxx Changes in v2: - Updated references to more recent standard IEEE802.1Q-2014. - Dropped reference to web link which might change in the future. - Typo fix in commit log. - Link to v1: https://lore.kernel.org/r/20241105-am65-cpsw-multi-rx-dscp-v1-0-38db85333c88@xxxxxxxxxx --- Roger Quadros (2): net: ethernet: ti: am65-cpsw: update pri_thread_map as per IEEE802.1Q-2014 net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX drivers/net/ethernet/ti/am65-cpsw-nuss.c | 100 +++++++++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw_ale.c | 36 ++++++----- 2 files changed, 122 insertions(+), 14 deletions(-) --- base-commit: 42f7652d3eb527d03665b09edac47f85fb600924 change-id: 20241101-am65-cpsw-multi-rx-dscp-000b2c4af6d0 Best regards, -- Roger Quadros <rogerq@xxxxxxxxxx>
