On Mon, Mar 04, 2024 at 04:36:01PM +0100, Thomas Richard wrote:
> From: Théo Lebrun <theo.lebrun@xxxxxxxxxxx>
>
> Add suspend and resume support. Only the rc mode is supported.
>
> During the suspend stage PERST# is asserted, then deasserted during the
> resume stage.
> + * "Power Sequencing and Reset Signal Timings" table in
> + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
> + * indicates PERST# should be deasserted after minimum of 100us
> + * once REFCLK is stable. The REFCLK to the connector in RC
> + * mode is selected while enabling the PHY. So deassert PERST#
> + * after 100 us.
Please cite current spec (r5.1 was published August 2023), section,
and parameter name. I think this is T_PERST-CLK, "REFCLK stable
before PERST# inactive", from sec 2.9.2.
> + */
> + if (pcie->reset_gpio) {
> + fsleep(100);
I'd like to see a macro used here instead of a bare number. Since
this isn't anything specific to j721e, maybe add something like
#define PCIE_T_PERST_CLK_US alongside PCIE_T_PVPERL_MS.
> + gpiod_set_value_cansleep(pcie->reset_gpio, 1);
> + }
