On Fri, Nov 24, 2023 at 12:41:33PM +0200, Tony Lindgren wrote:
> Commit 34539b442b3b ("bus: ti-sysc: Flush posted write on enable before
> reset") caused a regression reproducable on omap4 duovero where the ISS
> target module can produce interconnect errors on boot. Turns out the
> registers are not accessible until after a delay for devices needing
> a ti,sysc-delay-us value.
>
> Let's fix this by flushing the posted write only after the reset delay.
> We do flushing also for ti,sysc-delay-us using devices as that should
> trigger an interconnect error if the delay is not properly configured.
>
> Let's also add some comments while at it.
>
> Fixes: 34539b442b3b ("bus: ti-sysc: Flush posted write on enable before reset")
> Signed-off-by: Tony Lindgren <tony@xxxxxxxxxxx>
> ---
> drivers/bus/ti-sysc.c | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
Hi,
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