Hello, This series adds initial support for the Marvell PXA1908 SoC and "samsung,coreprimevelte", a smartphone using the SoC. USB works and the phone can boot a rootfs from an SD card, but there are some warnings in the dmesg: During SMP initialization: [ 0.006519] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU1: 0x00000000000000 [ 0.006542] CPU features: Unsupported CPU feature variation detected. [ 0.006589] CPU1: Booted secondary processor 0x0000000001 [0x410fd032] [ 0.010710] Detected VIPT I-cache on CPU2 [ 0.010716] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU2: 0x00000000000000 [ 0.010758] CPU2: Booted secondary processor 0x0000000002 [0x410fd032] [ 0.014849] Detected VIPT I-cache on CPU3 [ 0.014855] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU3: 0x00000000000000 [ 0.014895] CPU3: Booted secondary processor 0x0000000003 [0x410fd032] SMMU probing fails: [ 0.101798] arm-smmu c0010000.iommu: probing hardware configuration... [ 0.101809] arm-smmu c0010000.iommu: SMMUv1 with: [ 0.101816] arm-smmu c0010000.iommu: no translation support! On Samsung's PXA1908 phones, the bootloader does not start the ARM system timer, and my temporary solution (which isn't present in this series) was to put the code for starting the timer in the clock driver. Would this hack be accepted upstream in the form of a platform or clocksource driver such as drivers/clocksource/timer-mediatek-cpux.c? A 3.14 based Marvell tree is available on GitHub acorn-marvell/brillo_pxa_kernel, and a Samsung one on GitHub CoderCharmander/g361f-kernel. Andreas Färber attempted to upstream support for this SoC in 2017: https://lore.kernel.org/lkml/20170222022929.10540-1-afaerber@xxxxxxx/ Signed-off-by: Duje Mihanović <duje.mihanovic@xxxxxxxx> Changes in v7: - Suppress SND_MMP_SOC_SSPA on ARM64 - Update trailers - Rebase on v6.6-rc7 - Link to v6: https://lore.kernel.org/r/20231010-pxa1908-lkml-v6-0-b2fe09240cf8@xxxxxxxx Changes in v6: - Address maintainer comments: - Add "marvell,pxa1908-padconf" binding to pinctrl-single driver - Drop GPIO patch as it's been pulled - Update trailers - Rebase on v6.6-rc5 - Link to v5: https://lore.kernel.org/r/20230812-pxa1908-lkml-v5-0-a5d51937ee34@xxxxxxxx Changes in v5: - Address maintainer comments: - Move *_NR_CLKS to clock driver from dt binding file - Allocate correct number of clocks for each block instead of blindly allocating 50 for each - Link to v4: https://lore.kernel.org/r/20230807-pxa1908-lkml-v4-0-cb387d73b452@xxxxxxxx Changes in v4: - Address maintainer comments: - Relicense clock binding file to BSD-2 - Add pinctrl-names to SD card node - Add vgic registers to GIC node - Rebase on v6.5-rc5 - Link to v3: https://lore.kernel.org/r/20230804-pxa1908-lkml-v3-0-8e48fca37099@xxxxxxxx Changes in v3: - Address maintainer comments: - Drop GPIO dynamic allocation patch - Move clock register offsets into driver (instead of bindings file) - Add missing Tested-by trailer to u32_fract patch - Move SoC binding to arm/mrvl/mrvl.yaml - Add serial0 alias and stdout-path to board dts to enable UART debugging - Rebase on v6.5-rc4 - Link to v2: https://lore.kernel.org/r/20230727162909.6031-1-duje.mihanovic@xxxxxxxx Changes in v2: - Remove earlycon patch as it's been merged into tty-next - Address maintainer comments: - Clarify GPIO regressions on older PXA platforms - Add Fixes tag to commit disabling GPIO pinctrl calls for this SoC - Add missing includes to clock driver - Clock driver uses HZ_PER_MHZ, u32_fract and GENMASK - Dual license clock bindings - Change clock IDs to decimal - Fix underscores in dt node names - Move chosen node to top of board dts - Clean up documentation - Reorder commits - Drop pxa,rev-id - Rename muic-i2c to i2c-muic - Reword some commits - Move framebuffer node to chosen - Add aliases for mmc nodes - Rebase on v6.5-rc3 - Link to v1: https://lore.kernel.org/r/20230721210042.21535-1-duje.mihanovic@xxxxxxxx --- Andy Shevchenko (1): clk: mmp: Switch to use struct u32_fract instead of custom one Duje Mihanović (9): dt-bindings: pinctrl: pinctrl-single: add marvell,pxa1908-padconf compatible pinctrl: single: add marvell,pxa1908-padconf compatible dt-bindings: clock: Add Marvell PXA1908 clock bindings clk: mmp: Add Marvell PXA1908 clock driver ASoC: pxa: Suppress SSPA on ARM64 dt-bindings: marvell: Document PXA1908 SoC arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte MAINTAINERS: add myself as Marvell PXA1908 maintainer .../devicetree/bindings/arm/mrvl/mrvl.yaml | 5 + .../devicetree/bindings/clock/marvell,pxa1908.yaml | 48 +++ .../bindings/pinctrl/pinctrl-single.yaml | 4 + MAINTAINERS | 9 + arch/arm64/Kconfig.platforms | 11 + arch/arm64/boot/dts/marvell/Makefile | 3 + .../dts/marvell/pxa1908-samsung-coreprimevelte.dts | 333 +++++++++++++++++++++ arch/arm64/boot/dts/marvell/pxa1908.dtsi | 295 ++++++++++++++++++ drivers/clk/mmp/Makefile | 2 +- drivers/clk/mmp/clk-frac.c | 57 ++-- drivers/clk/mmp/clk-of-mmp2.c | 26 +- drivers/clk/mmp/clk-of-pxa168.c | 4 +- drivers/clk/mmp/clk-of-pxa1908.c | 328 ++++++++++++++++++++ drivers/clk/mmp/clk-of-pxa1928.c | 6 +- drivers/clk/mmp/clk-of-pxa910.c | 4 +- drivers/clk/mmp/clk.h | 10 +- drivers/pinctrl/pinctrl-single.c | 1 + include/dt-bindings/clock/marvell,pxa1908.h | 88 ++++++ sound/soc/pxa/Kconfig | 2 +- 19 files changed, 1178 insertions(+), 58 deletions(-) --- base-commit: 05d3ef8bba77c1b5f98d941d8b2d4aeab8118ef1 change-id: 20230803-pxa1908-lkml-6830e8da45c7 Best regards, -- Duje Mihanović <duje.mihanovic@xxxxxxxx>
