From: Li Chen <lchen@xxxxxxxxxxxxx>
I observed that on Ambarella SoC, which also utilizes
the Cadence controller, the boot time increases by 1
second when no endpoints (including switch) are connected
to PCIe. This increase is caused by cdns_pcie_host_wait_for_link.
Enabling async probe can eliminate this boot time increase.
I guess j721e also has this issue.
Signed-off-by: Li Chen <lchen@xxxxxxxxxxxxx>
---
drivers/pci/controller/cadence/pci-j721e.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index e70213c9060a..660c13bdb606 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -561,6 +561,7 @@ static struct platform_driver j721e_pcie_driver = {
.name = "j721e-pcie",
.of_match_table = of_j721e_pcie_match,
.suppress_bind_attrs = true,
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
};
builtin_platform_driver(j721e_pcie_driver);
--
2.34.1
